Semiconductor storage device and test system

ABSTRACT

A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with a computing circuit for generating an address signal for test; a packet decoder for designating the kind of computation to the computing circuit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device and atest system and, mainly, a technique effective for use in a technique ofa probing test on a dynamic RAM (Random Access Memory).

BACKGROUND ART

An example of a memory integrated circuit capable of realizing thefunctions of a timing margin test, a voltage margin test, and detectionof abnormal current by built-in functions is disclosed in thepublication of Japanese Unexamined Patent Application No. Hei8(1996)-315598. A memory integrated circuit of the publication hastherein a built-in test function (BIST) unit for generating a memorytest signal and various control signals, a timing generation circuit anda voltage generation circuit which are controlled by an output signal ofthe sequence unit, and a current sensor for detecting an abnormalcurrent, in which a current-to-voltage converting circuit and ananalog-to-digital converting circuit are connected in series.

In the memory integrated circuit having therein, in addition to the testbuilt-in function unit, timing generation circuit, a voltage generationcircuit, a current-to-voltage converting circuit, and a current sensor,the scale of the test circuit occupying the memory integrated circuit islarge; and, moreover, since the test circuit is used only at the time ofa test, there are problems in that the chip size is enlarged, in termsof storage bits as the inherent function of the memory integratedcircuit, and the current consumption is increased. The publicationindicates that the problems of the circuit scale and the like are solvedby a relative decrease in the test circuit area in association with afiner circuit and an increase in the capacity of the memory. However, itis not realistic to allow a large-scale test circuit, as describedabove, to be built in a general memory, such as dynamic RAM havingstorage capacity of about 64 Mbits or 256 Mbits as practically used atpresent.

The throughput of a probing test on a dynamic RAM or the like isdetermined by test time per chip and the number of chips (the number ofchips simultaneous measured). The number of chips simultaneous measuredis, however, under constraints of each of various hardware. For example,the number of bonding pads of a synchronous DRAM (Dynamic RAM) of 64Mbits is equal to at least 60 to 70 which is the sum of about 54 ofexternal terminals except for NC pins and special pads used for aprobing test.

On the other hand, the maximum number of needles of a probe card to beelectrically connected to the bonding pads is about 1,000 to 1,500.Accordingly, the maximum number of devices to be measured simultaneouslyis about 20. When the number of devices to be simultaneously measuredincreases, the number of generating times of signals, the number ofcomparators, and the number of power units on the tester side are alsoincreased, thereby raising the price of the tester. Further, it causesproblems such that the cost of a multi-needle probe card increases andthe life becomes shorter. Consequently, it is not easy to increase thenumber of devices to be simultaneously measured.

The inventors of the present invention have therefore examined solutionof the problems while minimizing the number of needle pads used for aprobing test. In association with the increase in the diameter of awafer in recent years, the number of memory chips obtained isconspicuously increasing. It is estimated that the number of chips to besimultaneously measured has to be increased more and more. As methods ofdecreasing the number of needle pads at the time of a probing test,reduction in the number of power source needle pads, reduction in thenumber of data input/output pads, reduction in the number of addressinput pads, and reduction in the number of clock input pads can bementioned. The power source pads can be eliminated by connecting thepower source in a memory chip except for a pair of VCC and VSS as longas the characteristics can be maintained. If the address input pads andclock input pads are eliminated, however, tests of reading and writingdata from/to a memory by designating an address cannot be conducted. Amethod of designating memory access patterns such as matching patternsby a simple control from the outside and generating them on the insidemay be considered. It is, however, estimated that the logic in the chipbecomes large and complicated, it causes an increase in chip size anddeterioration in yield, and the method does not contribute to reductionin cost as a total.

An object of the invention is, therefore, to provide a semiconductormemory device and a test system capable of conducting a memory test witha simple configuration. Another object of the invention is to provide asemiconductor memory device and a test system capable of conducting aprobing test with a smaller number of needle pads. Further anotherobject of the invention is to provide a semiconductor memory device anda test system capable of simultaneously measuring the increased numberof chips. The above and other objects and novel features of theinvention will become apparent from the description of the specificationand the attached drawings.

DISCLOSURE OF THE INVENTION

A representative technique of the present invention disclosed in thespecification will be briefly described as follows. A memory circuithaving a memory cell array in which a plurality of memory cells areprovided at intersection points of a plurality of word lines and aplurality of bit line pairs and a peripheral circuit for performing anoperation of selecting an address is provided with: an arithmetic unitwhich is also called an arithmetic circuit, a computing unit or acomputing circuit below for generating an address signal for a test onthe memory circuit; a packet decoder for designating the kind ofoperation on the arithmetic unit; and an input circuit for supplying atest signal comprising a plurality of bits for designating a testoperation to the packet decoder.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram related to a test circuit of an example of asemiconductor memory device according to the invention;

FIG. 2 is a timing chart showing an example of an input protocol of testsignals in the semiconductor memory device according to the invention;

FIG. 3 is a diagram for explaining bit patterns corresponding to theformat A of FIG. 2 and their operations;

FIG. 4 is a diagram of the structure of pads of an SDRAM according tothe invention as an example;

FIG. 5 is a block diagram showing an example of a test circuit mountedon the SDRAM according to the invention;

FIG. 6 is a circuit diagram showing an example of a packet control PCand a data input buffer DIB of FIG. 5;

FIG. 7 is a circuit diagram showing an example of a packet decoder PDECin FIG. 5;

FIG. 8 is a circuit diagram showing an example of an arithmetic circuitALU in FIG. 5;

FIG. 9 is a waveform chart for explaining the operation of thearithmetic circuit ALU in FIG. 8;

FIG. 10 is a schematic layout sketch showing an example of the SDRAMaccording to the invention;

FIG. 11 is a schematic layout sketch showing an example of the SDRAMaccording to the invention;

FIG. 12 is a circuit diagram showing a simplified example starting fromaddress input until data output and mainly illustrating a senseamplifier of the SDRAM according to the invention;

FIG. 13 is a general block diagram showing an example of the SDRAMaccording to the invention; and

FIG. 14 is a schematic sketch for explaining a test system according tothe invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The invention will be described in more detail with reference to theattached drawings.

FIG. 1 is a block diagram related to a test circuit of an example of asemiconductor memory device according to the invention. The embodimentis directed to, although not particularly limited, a synchronous dynamicRAM (which may be simply called an SDRAM hereinbelow).

An SDRAM core includes peripheral circuits such as a memory array and anaddress selection circuit. The SDRAM has, in addition to the above, an Xaddress latch, a Y address counter, a mode register, a timing generator,and a vendor test. By controlling the components by a packet decoder anda pattern generation controlling circuit which construct a test circuit,a probing test is carried out.

In I/O (input/output) terminals provided in correspondence with theSDRAM core, four data input/output terminals DQ0 to DQ3 are used asterminals of input and output signals for test. A pad CKEP used for modeentry in control signals, a clock terminal CLK, and a chip selectterminal CS/ are used to receive test signals from the terminals DQ0 toDQ3.

Only a pair of a source voltage terminal VCC for supplying a power andan earth terminal VSS of the circuit are used for a test. A pad VPP(step-up voltage), a pad VBB (substrate back-bias voltage), and padsVDLP, VDLA, VPLT, and VBLR (internal step-down voltage) for monitoringan internal voltage are provided for a probing test. As a result, in theSDRAM of the embodiment, irrespective of the storage capacity of about64 Mbits as will be described hereinlater, the number of electrodes(pads) used for a test can be decreased to 15.

In the embodiment, test signals of four bits supplied from the datainput/output terminals DQ0 to DQ3 are formed as a packet (packet ofinformation), and setting of all of operation controls for testing theSDRAM is realized by a single test signal or a combination of testsignals. The test signal is supplied to a packet decoder where the bitpattern is decoded. For example, the pattern generation control circuitgenerates and supplies an X address signal for selecting a word line tothe X address latch, and generates and supplies a Y address forselecting a bit line to the Y address counter.

By combinations of test signals of four bits (one packet), 16 controlsignals can be generated at the maximum. By combining a part (n) of thecontrol signal and the next packet, (n×16) control signals can begenerated. Further, by combining unused parts (m) in the above twopackets, (m×16) control signals can be generated. It is sufficient togenerate all of control signals necessary for operations of testing amemory circuit.

To determine whether input signals supplied from the data input/outputterminals DQ0 to DQ3 are the test signal or not, the pad CKEP is used.Specifically, by combining this signal CKEP, the clock signal CLK, andthe chip select signal CS/, the data input signal in normal operationand a test signal in test operation are discriminated from each other.

With such a configuration, the number of pads necessary for electricalcontact at the time of a testing operation is largely reduced to 15 permemory chip. By decreasing the number of contact pads in such a manner,the number of memory chips contacted simultaneously with a conventionalprobe card can be largely increased. The test time can be substantiallylargely shortened.

While increasing the number of chips to be measured simultaneously, andwhile assuring all of testing operations necessary for an operation teston a memory circuit by serially inputting one or a plurality of testsignals as a packet, in order to make setting of an operation test athigh speed, the following is devised.

The four data input/output terminals DQ0 to DQ3 are also used foroutputting a test result. Although not particularly limited, the SDRAMhas four memory banks, and a test is conducted by simultaneouslyoperating the four memory banks. The test result generated every memorybank is outputted through the data input/output terminals DQ0 to DQ3.Therefore, test read data of every four memory banks is outputted andcompared with an expectation value by an external tester.

Using four bits of signals to conduct a test is very convenient for theSDRAM. From the viewpoint of a testing operation, two bits areinsufficient as information for setting a testing operation, as will bedescribed hereinlater. A bit pattern of eight bits is too large, so thata waste occurs, and the number of test terminals increases.

FIG. 2 is a timing chart of an example of an input protocol of testsignals in a semiconductor memory device according to the invention.

In the embodiment, although not particularly limited, three formats A toC are prepared. The first format A is constructed by one cycle (onepacket) in which an operation command of a high use frequency is set.The second format B is constructed by two cycles (two packets) in whichan operation command of a low use frequency is set. The third format isconstructed by four cycles (four packets) and is used to set variousregisters in a memory by combining two second formats.

In the first format A, an input mode of a test signal is designated bythe high level of the clock CKEP, the high level of the clock signalCLK, and the low level of the chip select signal CS/. A packet decodercorresponding to the first format A receives a four-bit test signal(first primary signal) RP1 entered as a command itself from the datainput/output terminals DQ0 to DQ3, decodes it, and starts operationST/OP immediately in the second cycle.

In the second format B, similarly, by the high level of the signal CKEP,the high level of the clock signal CLK, and the low level of the chipselect signal CS/, an input mode of the test signal is designated. Thechip select signal CS/ is set to the low level for two cycles. A packetdecoder corresponding to the second format B discriminates that afour-bit signal entered from the data input/output terminals DQ0 to DQ3as the test signal (first primary signal) RP1 is “OTHR” (refer to thefollowing), receives a four-bit test signal (second primary signal) RP2entered in the second cycle as a command, decodes the test signal RP2,and starts operation ST/OP in the third cycle.

In the third format C, similarly, by the high level of the signal CKEP,the high level of the clock signal CLK, and the low level of the chipselect signal CS/, the input mode of the test signal is designated. Thechip select signal CS/ is set to the low level twice each time for twocycles. A packet decoder corresponding to the third format Cdiscriminates that the four-bit test signal (first primary signal) RP1entered from the data input/output terminals DQ0 to DQ3 is set to “OTHR”(refer to the following), receives the four-bit test signal (secondprimary signal) RP2 entered in the second cycle as information of adesignated register, discriminates that a four-bit test signal (firstsecondary signal) RS1 entered in the third cycle is set to “REG”(register mode), receives a four-bit test signal (second secondarysignal) RS2 entered in the fourth cycle as a command, and performs anoperation on the register designated in the second cycle.

In the case of using the test signals (packets) as the primary (first)signals in two cycles and the secondary (latter) signals in two cycles,the configuration of the packet decoders can be made simpler as will bedescribed hereinlater. In other words, by constructing the decoder intwo stages in correspondence with the two cycles, the formats B and Ccan be constructed by similar circuits. The format A can bediscriminated from the format B by the combination with the chip selectsignal CS/. In the format A, a command can be executed from the secondcycle.

FIG. 3 is a diagram for explaining bit patterns corresponding to theformat A in FIG. 2 and their operations.

To the format A, five commands of NOP (no operation), PRE (precharge),READ (read), WRIT (write), and ACTV (bank active) of a high usefrequency in operation commands of an SDRAM are assigned. The READ andWRIT commands are accompanied with a column (Y) address control, and theACTV command is accompanied with a row (X) address control.

For each of the three commands READ, WRIT, and ACTV, four kinds ofaddress controls are performed. Specifically, in each of the commandsREAD and WRIT, “0” denotes that the Y address is set to 0, “hold”denotes that the address Y of the current cycle is held, +BL denotesthat a value BL set in the register is added to the address Y of thecurrent cycle (Y+BL), and −BL indicates that the value BL set in theregister is subtracted from the address Y of the current cycle. In theACTV command as well, in a manner similar to the above, “0” denotes thatthe X address is set to “0”, “hold” denotes that the address X of thecurrent cycle is held, +XL denotes that a value XL set in the registeris added to the address X of the current cycle (Y+BL), and −XL denotesthat a value XL set in the register is subtracted from the address X ofthe current cycle (X−XL).

By the command as described above, 14 bit patterns are used by the testsignal (packet) of four bits. To the remaining two bit patterns, theabove-described command “OTHR” instructing reference to the next packetand “REG” instructing a register mode are assigned.

In the format B, operation commands having not so high use frequency inthe operation commands of the SDRAM, for example, eight commands of PALL(all bank precharge), CBR (automatic refresh), SELF (self refresh), BST(burst stop), PWRDN (power down mode), SELFX (self refresh end), andmode setting such as “auto precharge enable” and “auto precharge modedisable” are assigned. Although the bit patterns of the test signal RP2with respect to the commands will not be described, 16 commands can bedesignated at the maximum by the combination with the test signalRP1=OTHR. Consequently, after assigning the above eight commands, eightcommands are still available and can be used for setting the kind of aregister of the format C.

In the format C, although each of the bit patterns will not bedescribed, in the test signal RP2, any of the operation commands of theSDRAM is used as register setting. For example, setting of a moderegister, selection of a bank, setting of a vendor test, or trimmingselect of VPP, VDLA, or VDLP is assigned. In the secondary test signalRS1, by combination with the test signal RS1 (=RP1) =REG, 16 registeroperations at the maximum with respect to each of the registersdesignated by the test signal RP2 can be set.

FIG. 4 is a diagram of the structure of pads of an SDRAM according tothe invention as an example. In an SDRAM, pads corresponding toterminals to be connected with external terminals and pads used for aprobing test are formed. Pads to be connected to external terminals aremounted on a package of 54 pins including three pairs of power sourceterminals *VCC and *VSS on both ends and the center of the package andtwo pairs of *VCCQ and *VSSQ for output circuit. As pads used for thetest circuit according to the invention, as shown in FIG. 1, 15 pads areused which are the clock CLK, chip select CS/, data input/output DQ0 toDQ4, power sources VCC and VSS to be connected to the external terminalsand, in addition, the substrate potential VBB, word line step-up voltageVPP, peripheral circuit potential VDLP, array potential VDLA, bit lineprecharge potential VBLR, plate potential VPLT, and mode entry pad CKEP.

That is, out of about 60 pads formed on an SDRAM, electrical contact ismade on the 15 pads to conduct an operation test on a memory circuit.

Conversely, electrical contact is not made on the control terminals CKE,RAS/, CAS/, and WE/ and, in addition, the address terminals A0 to A13,the data input/output terminals DQ4 to DQ15, power source terminals VCCQand VSSQ for output circuit, and mask terminals DQMU and DQML forinput/output circuit with a blank in the option-3. By the test signal(packet) entered from the data input/output terminals DQ0 to DQ3,internal signals such as an operation command and an address signal ofan SDRAM are generated.

FIG. 5 is a block diagram showing an example of a test circuit to bemounted on the SDRAM according to the invention.

The test circuit includes a plurality of packet decoders provided incorrespondence with circuits to be tested. Particularly, when a circuitto be tested is a row address latch XAD-L, as well as a packet decoderPDEC2, an arithmetic circuit ALU2 for generating a row address signal isadded. To a column address counter YCNT, as well as a packet decoderPDEC1, an arithmetic circuit ALU1 for generating a column address signalis added.

For the computing circuit ALU2, a sub register s-xreg is provided. Byusing a configuration such that one of registers xreg and s-xreg isswitched and connected to the computing circuit ALU2 and by allowing thesub resister s-xreg to generate a refresh address, switching between atest address and a refresh address can be easily made. It is alsopossible to use both of the two resisters for a testing operation andperform non-continuous address switching.

For a timing generator, a packet decoder PDEC3 is provided. For moderegisters MRG1 and MRG2, packet decoders PDEC4 and PDEC5 are provided,respectively. For a timing generator TREG, a packet decoder PDEC6 isprovided. In such a manner, a packet decoder is provided for each of thecircuits necessary for a control for the testing operation, and thepacket decoders PDEC1 to PDEC6 are connected to a data bus DBUS and aclock bus CBUS, in parallel.

Test signals entered from the data input/output terminals DQ0 to DQ3 arereceived via a data input buffer DIB and transferred to the data busDBUS. Each of the packet decoders PDEC1 to PDEC6 therefore receives theentered test signal and, while discriminating whether the test signal isthe command assigned to itself or not, executes the command.

A packet control PC receives signals from the mode entry pad CKEP, clockterminal CLK, and chip enable terminal CS/ and transmits a clock signalto the clock bus CBUS. Two out of four lines of the clock bus CBUS areused for clock signals JJB and KKB each obtained by frequency dividingthe clock signal to the half. Synchronously with the clock signal JJP,the signals RP1 and RS1 are entered. Synchronously with the clock signalKKB, the signals RP2 and RS2 are entered.

The circuits for a test operation are spread to the circuit blocksnecessary to be controlled as in the embodiment and simple circuits suchas the packet decoders are provided adjacent to the circuits, therebyenabling gaps and empty spaces between circuit blocks to be utilizedfrom the viewpoint of layout. Consequently, a substantial increase inchip area can be prevented.

FIG. 6 is a circuit diagram showing an example of the packet control PCand the data input buffer DIB in FIG. 5.

The data input buffer DIB has a data latch circuit for latching signalsentered from the data input/output terminals DQ0 to DQ3. By theconditions of the low level of the chip select signal CSB (CS/) and thehigh level of the mode entry pad CKEP, a transfer MOSEET provided at anoutput section of the data latch circuit is turned on, and the enteredsignal is sent as a test signal to the data bus DBUS. The data latchcircuit is constructed by a transfer gate MOSFET for transmitting aninput signal to a serially connected CMOS inverter circuit and atransfer gate MOSFET for feedback which latches the CMOS invertercircuit.

The packet control PC takes the form of a binary counter circuit byusing two through latch circuits similar to the above, and is madeoperative by the CKEP and CSB to perform an operation offrequency-dividing an input clock signal CLK, thereby generatingtwo-phase clock signals JJB and KKB of which cycle is twice as many asthat of the clock signal CLK and which are alternately outputted.

FIG. 7 is a circuit diagram showing an example of the packet decoderPDEC in FIG. 5. In the diagram, decoders corresponding to the signalsRP1 (RS1) and RP2 (RS2) are shown.

In the decoder corresponding to the format A, the signals READ, WRIT,and ACTV are generated by gate circuits for receiving signals PK2B andPK3B of the upper two bits from packet signals PK0B to PK3B of four bitssupplied via the data input buffer DIB. The signals PK0B and PK1B of thelower two bits are decoded by gate circuits (not shown) and fourcommands (0, hold, + and −) are added to the signals READ, WRIT, andACTV. An address control as described above using the arithmetic circuitALU is also added. The commands of the precharge PRE, no operation NOP,other OTHR, and register mode REG are generated by the gate circuits forreceiving the four-bit signals PK0B to PK3B. The clock signal JJB issupplied to the gate circuits for generating the commands, and inputsignals entered in the first and third cycles are decoded.

The signal OTHR is latched by the latch circuit on the basis of theclock signal JJB, and the operations of the gate circuits correspondingto the packet signals PK0B to PK3B are made effective by the signal OTHRand the clock signal KKB subsequently entered. By the gate circuits,signals of the commands PALL, CBR, SELF, BST, PWRDN, SELFX, APEN (autoprecharge enable), and APDE (auto precharge disable) corresponding tothe format B are generated. The signals APEN and APDE are supplied to alatch circuit constructed by a gate circuit where the auto prechargesignal AP is generated.

Although not shown, in correspondence with the format C, a register isdesignated by combination of the remaining signals RP2, the command REGis generated by the signal RS1 supplied synchronously with the clocksignal JJB of the next cycle, and a signal for operating the register isgenerated by a gate circuit for decoding the packet signals PK0B to PK3Bsupplied synchronously with KKB.

A plurality of gate circuits as described above are not constructed asone packet decoder. For example, the gate circuit for generating thecommands READ and WRIT is included in the packet decoder PDEC1 providedadjacent to the column address counter shown in FIG. 5, and the gatecircuit for generating the command ACTV is provided adjacent to the rowaddress latch XAD-L shown in FIG. 5. The circuits for generating thecommands are provided so as to be spread in the circuit blockscorresponding to the respective functions. As described above, thepacket decoder is constructed by a simple gate circuit. By disposing thepacket decoders so as to be spread to circuits to be controlled, gapsand empty spaces between circuit blocks can be utilized from theviewpoint of a layout. Consequently, a substantial increase in chip areacan be prevented.

FIG. 8 is a circuit diagram showing an example of the arithmetic circuitALU in FIG. 5. In the example, a circuit of four bits is illustrated asa representative. The arithmetic circuit ALU in the example is togenerate a row (X) address signal and a column (Y) address signal for atesting operation as described above. By limiting the function of thecomputing circuit ALU to generation of an address, therefore, attempt ismade to simplify the circuit.

Specifically, an address signal for the testing operation issufficiently generated by not only simple increase or decrease in anaddress such as +1 or −1 but also setting of addresses of a discretenumber such as +2 or −2. In the example, the function of adding orsubtracting a discrete number such as +4 or −4 is also added. Bycombining the functions, an address can be designated in a wide range.By adding “clear (0)” and “hold” for holding the preceding state,designation of all of addresses for a testing operation can be achieved.

By limiting the numbers of addition and subtraction to, for example, 1,2, and 4 as described above, in an actual arithmetic circuit, anarithmetic circuit for each of the lower three bits can be realized by asimple circuit similar to a half adder for inverting a value andgenerating a carry when both of a value before addition and a value tobe added are “1” or inverting the value before addition when it is 0 inan adding operation.

Specifically, two through latch circuits are connected in series, a gatecircuit is used as the through latch circuit on the input side and iscontrolled by a control signal ZERO so that all of outputs of the latchcircuit at the front stage are forcedly set to 0. The output signals Q0to Q3 of the latch circuit on the output side and the like are fed backto the input side and used to control two pairs of transfer gatecircuits. The first pair of transfer gate circuits is used to generatean addition output of the bit. With respect to the least significantbit, when both an addition signal AD1 and the output Q0 are “1”, “0” isgenerated, and a carry is generated through the second pair of transfergate circuits. When either the addition signal AD1 or the output Q0 is“1”, the original values are used.

An adding operation is performed by operating the two latch circuits bya control signal PLUS to thereby generate the addition signal. Asubtracting operation is realized by controlling the second pair oftransfer gate circuits by a control signal MINUS to generate complementnumbers such as the outputs Q0 to Q3, and adding addition signals AB2and AB4. When a control signal HOLD becomes effective, control signalsLS/ and LS of the latch circuit on the rear side are generated, andunchanged signals of the latch circuit on the front side are received asthey are.

In the example, as a precondition, a simplified circuit as describedabove is used as the arithmetic circuit, and only one of the additionsignals AB1, AB2, and AB4 becomes “1”. The result of computation when anaddition signal of 2 or larger is set to 1 by mistake is not thereforeguaranteed. Although it is imperfect as a computing circuit, when theuse is limited to generation of an address signal for a testingoperation, the drawbacks are not so considered since the test circuit isused by a semiconductor manufacturer who knows the function very well.It is unnecessary to consider the case where the circuit is erroneouslyused.

FIG. 9 is a waveform chart for explaining an example of the operation ofthe arithmetic circuit.

When the control signal ZERO goes high, an output of the NOR gatecircuit in the latch circuit on the front side in the computing circuitbecomes 0, the clock signals LS and LS/ are generated and latched by thelatch circuit on the output side, and all of the address signals become0.

When the addition signal AB1 is set to the high level (1), an outputnode X0 of the first pair of transfer gate circuits becomes 1. When thecontrol signal PLUS goes high, the clock signals LS and LT aregenerated, and an output node Y0 of the latch circuit on the front sidebecomes 1 in correspondence with 1 of the output node X0. When thecontrol signal PULS goes low, the clock signal LS also changes, and anoutput signal Z0 (Q0) of the latch circuit at the rear side changesto 1. By the change in the output signal Z0, the two transfer gatecircuits are switched, the output node X0 is changed to the low level“0” and the next bit X1 is changed to “1”. Subsequently, when thecontrol signal PLUS is set to the high level, the clock signals LS andLT are generated in a manner similar to the above, and the output nodeY0 of the latch circuit on the front side is changed to “0”, and theoutput node Y1 is changed to “1”. When the control signal PULS goes low,the clock signal LS also changes, and the output signal Z0 (Q0) of thelatch circuit on the back side is changed to 0, and the output signal Z1(Q1) is changed to 1. In such a manner, the address signal increases by+1 each time. The addition signal AB1 is returned to the low level forthe next operation.

When the control signal HOLD goes high, only the clock signal LS isgenerated, signals from the output nodes Y0 to Y3 and the like of thelatch circuit on the front side are supplied to the latch circuit on theback side. Since the previous state is received as it is, no changeoccurs in outputs Z0 to Z3 (Q0 to Q3) and the like.

When the addition signal AB2 is set to the high level, in the secondbit, the output node X1 is changed to the low level “0”, and the nextbit X2 is changed to “1”. Subsequently, when the control signal PLUS isset to the high level, in a manner similar to the above, the output nodeY1 in the latch circuit at the front side changes to 0, and the outputnode Y2 changes to 1. When the control signal PULS goes low, the clocksignal LS also change, the output signal Z1 (Q1) of the latch circuit onthe back side changes to 0, the output signal Z2 (Q2) changes to 1, andaddition of +2 is executed.

When the addition signal AB2 goes low and the addition signal AB1 goeshigh, the output node X0 changes to the high level. When the controlsignal MINUS is set to the high level, the outputs Z0 to Z2 (Q0 to Q2)of the lower three bits are inverted, complement numbers are generated,and +1 of the AB1 is added. Consequently, the result of subtraction of−1 is derived. When the addition signal AB1 goes low, the additionsignal AB2 goes high, and the control signal MINUS goes high, theoutputs Z0 to Z2 (Q0 to Q2) of the lower three bits are inverted, acomplement number is generated, +2 of the addition signal AB2 is added,and the result of subtraction of −2 is generated. Similarly, when thecontrol signal HOLD is set to the high level, the result of calculationis maintained. When the control signal ZERO is generated, all of theoutputs Z0 to Z3 and the like are cleared to 0.

For example, when an address step is set to +3, it can be realized byperforming two cycles of +1 and +2, or two cycles of +4 and −1. Theaddress step operation except for ±1, ±2, and ±4 can be arbitrarily setby the combination. An address can be generated in the testing operationby a relatively simple pattern. It can sufficiently correspond to thelimited computing function as described above.

FIG. 10 is a schematic layout sketch showing an example of the SDRAMaccording to the invention. Each circuit block in the diagram is formedon a single semiconductor substrate made of single crystal silicon orthe like by a known technique of fabricating a semiconductor integratedcircuit. The circuits in the diagram are drawn almost in accordance witha geometrical arrangement on the semiconductor substrate. In theembodiment, a memory array is divided into four pieces and memory banksBank0 to Bank3 are formed.

The memory banks 0 to 3 are disposed in correspondence with the memoryarray divided into four pieces of two pieces each in the upper and lowersides and two pieces each in the right and left sides. In the centerportion in the longitudinal direction of the chip, peripheral circuitsincluding an address input circuit, and a data input/output circuit, anda line of bonding pads are provided. In the peripheral circuits, torationalize the layout of the circuits which take the form of randomlogic circuits, the random logic circuits and bonding pads are disposedin parallel to each other.

In the example, the peripheral circuits and the bonding pad line arearranged in parallel to each other. In the configuration, the bondingpad line is disposed in a position deviated from the center line in thelongitudinal direction of the semiconductor chip. As a result, in thecenter portion in the longitudinal direction of the semiconductor chip,a relatively large area can be assured, so that it is convenient todesign the layout of the circuit device. That is, the configurationwhere the peripheral circuits and the bonding pad line are arranged inparallel is suitable for higher packing density and higher processingspeed as compared with a configuration where peripheral circuits aredisposed on the right and left sides of bonding pads as a center.

The next circuit block is provided in the center portion of the upperhalf in the longitudinal direction of the semiconductor chip in FIG. 10.VPP-G denotes a step-up voltage generating circuit used for an operationvoltage of a selection circuit of a word line to which a memory cell isconnected and a selection circuit of a shared switch MOSFET which willbe described hereinlater to determine a selection level. VPP-C denotes acontrol circuit for controlling operations of the step-up voltagecircuit.

HVCCQ-G indicates a circuit for generating a voltage obtained bydividing the source voltage VCC to the half. The obtained voltage isused as a reference voltage of an input buffer constructed by adifferential circuit to determine the level (high or low) of an inputsignal of VCC amplitude. IOB and CL-C denote an input/output circuit anda clock control circuit, respectively. CL-C is used for an operationcontrol adapted to CAS latency of an output buffer. Five sets of IOB andCL-C having similar circuit configurations are provided as a whole.

Y-PRED and RWB express a Y predecoder and a read/write buffer,respectively. The read/write buffer performs an operation control of amain amplifier and an operation of a sense amplifier. VDLP-G and VDLA-Gdenote step-down voltage generating circuits and generate a step-downoperation voltage VDLP of the peripheral circuits and an operationvoltage VDLA of a sense amplifier, respectively. Two more step-downvoltage generating circuits similar to the above are provided. VPP-Sdenotes a VPP sensor for detecting whether a VPP voltage is a desiredvoltage or not. In the center portion of the semiconductor chip, astabilization capacitor VPERI-C for stabilizing the step-down voltageVPERI is provided.

In the center portion of the lower half in the longitudinal direction ofthe semiconductor chip in the diagram, the following circuit blocks areprovided. XAD-L denotes an X address latch circuit, Y-CLK indicates a Yclock circuit for generating a clock signal corresponding to a Yoperation. MDEC/CLKB and COMD denote a mode decoder/clock buffer and acommand circuit, respectively. ADMR denotes an address mode register.One more similar circuit is provided. Y-CNT and Y-CNC denote a Y counterand its control circuit, respectively. REFC denotes a refresh controlcircuit, BOP expresses a bonding option circuit, and PUP-G denotes apower-on detection circuit.

Along the plurality of circuit blocks as described above, bonding padsare arranged almost linearly. In the configuration, a signaltransmission route in the circuit blocks is not made long undesirably toavoid the bonding pads but can be formed in shorter length as comparedwith the configuration where the periphery circuits ae disposed on theright and left sides. Consequently, the operation can be performed athigher speed. Since one circuit block can be formed so as to beconcentrated in a large area, the layout of the circuit device on whichautomatic wiring is considered to be conducted is facilitated.

The test circuits are provided so as to be spread into the circuitblocks. For example, a circuit for capturing the four-bit test signal isadded as shown by a hatched portion in IOB-CLC. The addition circuitALU2 and a packet decoder corresponding to the circuit are disposed nextto the address latch circuit XAD-L. The addition circuit ALU1 and apacket decoder corresponding to the circuit are provided next to thecolumn address counter YCNT. MDEC/CLKB and COMB is also provided with apacket decoder designated by the packet signal. As described above, thetest circuit is formed by dispersing its circuits to the circuit blockshaving the circuit functions of the peripheral circuits, an increase inchip size can be prevented.

In the center portion in the minor-axis direction of the semiconductorchip, other peripheral circuits BSLOWER are provided. In the circuitBSLOWER, although not particularly limited, as will be described, adefect repair circuit for replacing a defect in a memory array (memorybank), that is, a defective word line with a spare word line orreplacing a defective bit line with a spare bit line is provided.

FIG. 11 is a schematic layout sketch showing an example of the SDRAMaccording to the invention. In the diagram, the memory array is mainlydrawn, which is divided into four memory arrays as a whole. Two memoryarrays are disposed in each of the upper and lower sides in thelongitudinal direction of the semiconductor chip and two memory arraysare disposed in each of the right and left sides. In a manner similar tothe above, an input/output interface circuit PERI including an addressinput circuit, a data input/output circuit, and a bonding pad line isprovided in the center portion along the longitudinal direction of thechip. In the center side of the memory arrays, main amplifiers MA aredisposed.

In the total four memory arrays of two each on the upper and lower sidesand two each on the right and left sides in the longitudinal directionof the semiconductor chip, in an intermediate portion in the lateraldirection with respect to the longitudinal direction, an X predecodercircuit ROWPDC, an X repair circuit ROWRED, a Y predecoder circuitCOLPDC, and a Y repair circuit COLRED are arranged in a lump. That is,two sets of the X predecoder circuits ROWPDC, X repair circuits ROWRED,Y predecoder circuits COLPDC, and Y repair circuits COLRED are providedin correspondence with the four memory arrays in which two each areprovided on the right and left sides.

In a manner similar to the above, main word driver areas MWD are formedin the intermediate portion between the memory arrays, and main wordlines provided so as to extend in the vertical direction are driven. Inthe configuration, in the case of using sub-arrays as described above,the main word line is extended so as to penetrate 16 sub-arrays. In thememory arrays, on the chip peripheral side opposite to the centerportion of the chip, Y decoders YDC are provided. In the embodiment, thefour memory arrays are disposed so as to be sandwiched by the mainamplifiers MA disposed in the center side and the Y decoders YDCdisposed on the peripheral sides. In this case, in the center area ofthe chip, there is a portion where interconnection channels extended inthe vertical and lateral directions cross each other, and astabilization capacitor C is formed in the portion. Stabilizationcapacitors each having a small capacitance value are properly providedso as to be spread in gaps in the peripheral circuits as describedabove.

In the memory arrays, although not particularly limited, the Y decodersYDC are provided on the chip peripheral sides opposite to the chipcenter portion. In the embodiment, each of the four memory arrays isdisposed so as to be sandwiched by the main amplifier MA disposed on thecenter side and the Y decoder YDC disposed in the peripheral side. Eachof the memory arrays is divided into a plurality of sub arrays 15. Oneof the sub arrays 15 is enlargedly shown. The sub array 15 is surroundedby sense amplifier areas 16 and sub word driver areas 17 arranged so asto sandwich the sub array 15. The intersection portion of the senseamplifier area 16 and the sub word driver area 17 is an intersectionarea 18. A sense amplifier provided in the sense amplifier area 16 is ofa shared sense system. Except for sense amplifiers disposed at both endsof a memory cell array, complementary bit lines are provided on theright and left sides of the sense amplifier as a center and areselectively connected to either a right or left complementary bit lineof the memory cell array.

One sub array 15 is constructed by, for example, not-illustrated 256 subword lines and 256 pairs of complementary bit lines (or data lines)which perpendicularly cross the sub word lines. The sub array is alsoprovided with spare word lines and spare complementary bit lines forrepairing a defective word line or defective bit line. 16 sub arrays areprovided in the word line disposing direction in a single memory array.As a whole, the sub word lines of about 4K are provided. Since the 16sub arrays are provided in the bit line disposing direction, thecomplementary bit lines of about 4K are provided as a whole.

By selecting a sub word line and a pair of complementary bit lines ineach of the 16 sub arrays corresponding to the main word lines, a memoryaccess on the 16-bit unit basis is performed. As described above, 256pairs of complementary bit lines are provided in the sub array. A columnaddress signal such as A0 to A7 has eight bits. 256 sub arrays asdescribed above are provided in the bit line direction and 16 sub arraysare provided in the memory bank. The number of sub word lines istherefore equal to (256×16=) 4096, and the row address signal comprises12 bits as A0 to A11.

Since four such memory arrays are provided in an entire device, thestorage capacity of (4×4K×4K=) 64 Mbits can be achieved in total. Thelength of the complementary bit line is divided into 16 parts incorrespondence with the 16 sub arrays. The sub word line is divided into16 in correspondence with the 16 sub arrays.

A sub word driver (sub word line driving circuit) 17 is provided forevery sub array 15 as a part of the memory array. The sub word driver 17is divided into parts each having the length of {fraction (1/16)} of themain word line as described above and generates a selection signal of asub word line extending in parallel with it. In the embodiment, in orderto decrease the number of main word lines, in other words, in order tomake the wiring pitch of the main word lines lower, although notparticularly limited, four sub word lines are disposed in thecomplementary bit line direction per main word line. In order to selectone of the sub word lines each divided into eight pieces in the mainword line direction and four each are assigned in the complementary bitline direction, a sub word selection driver (not shown) is disposed inthe main word driver MWD. The sub word selection driver generates aselection signal for selecting one of the four sub word selection linesextending in the disposing direction of the sub word driver.

In the case of employing the layout as shown in FIG. 11, when a Yaddress is entered, it is transmitted through an address buffer ADDBUP,and the repair circuit and the predecoder provided between the memoryarrays to the Y decoder YDC disposed on the periphery side of the chipand the Y selection signal is generated. One of the sub arraycomplementary bit lines is selected by the Y selection signal and thesignal is transmitted to the main amplifier MA on the center side whichis the opposite side of the chip, amplified, and outputted through anot-illustrated output circuit.

In the configuration, it seems that time required for a signal passingthrough a chip until a read signal is outputted is long. It is, however,necessary to supply the address signal as it is to the repair circuit,when the repair circuit is disposed in the center portion of the chip,after determining whether the address is that of a defect or not, outputtime of the predecoder is determined. That is, when the predecoder andthe repair circuit are apart from each other, a signal delay between thepredecoder and the repair circuit causes a delay in an actual Yselection operation.

In the embodiment, since the main amplifier MA and the Y decoder YCD aredisposed on both sides of a memory array, the sum of a signaltransmission path for selecting the complementary bit line of the subarray and the signal transmission path starting from the selectedcomplementary bit line via an input/output line to the input of the mainamplifier MA is equal to the signal transmission path only crossing thememory array irrespective of selection of any complementary bit line andcan be reduced to the half of the path of one round trip as describedabove. Thus, the memory can be accessed at higher speed.

FIG. 12 is a diagram showing an example of a simplified circuit fromaddress input to data output and mainly showing a sense amplificationsection in the SDRAM according to the invention. In the diagram,circuits provided in the sense amplifier 16 and a cross area 18sandwiched by two sub arrays 15 from the upper and lower sides are shownas an example, and the other portions are shown as blocks.

One dynamic memory cell provided between a sub-word line SWL providedfor the sub array 15 and one (BL) of complementary bit lines BL and BLBis illustrated as an example. The dynamic memory cell includes anaddress selection MOSFET Qm and a storage capacitor Cs. The gate of theaddress section MOSFET Qm is connected to the sub word line SWL, thedrain of the MOSFET Qm is connected to the bit line BL, and the storagecapacitor Cs is connected to the source. The other electrode of thestorage capacitor Cs is commonly used and a plate voltage VPLT isapplied to the other electrode. A negative back bias voltage VBB isapplied to the substrate (channel) of the MOSFET Qm. Although notparticularly limited, the back bias voltage VBB is set to a voltage suchas −1V. The selection level of the sub word line SWL is set to the highvoltage VPP higher than the high level of the bit line only by theamount corresponding to the threshold voltage of the address selectionMOSFET Qm.

In the case of operating the sense amplifier by the internal step downvoltage VDLA, the high level amplified by the sense amplifier and givento the bit line is set to the internal voltage VDLA level. The highvoltage VPP corresponding to the selection level of the word line istherefore set to VDLA+Vth+α. The pair of complementary bit lines BL andBLB of the sub array provided on the left side of the sense amplifierare disposed in parallel to each other as shown in the diagram. Thecomplementary bit lines BL and BLB are connected to an input/output nodeof a unit circuit of the sense amplifier by shared switch MOSFETs Q1 andQ2.

The unit circuit of the sense amplifier takes the form of a CMOS latchcircuit including n-channel type amplification MOSFETs Q5 and Q6 andp-channel type amplification MOSFETs Q7 and Q8 in a latch form in whichthe gates and the drains are connected so as to cross each other. Thesources of the n-channel MOSFETs Q5 and Q6 are connected to a commonsource line CSN. The sources of the p-channel MOSFETs Q7 and Q8 areconnected to a common source line CSP. A power switch MOSFET isconnected to each of the common source lines CSN and CSP. Although notparticularly limited, an operation voltage corresponding to the groundpotential is applied by an n-channel power switch MOSFET Q14 provided inthe cross area 18 to the common source line CSN to which the sources ofthe n-channel amplification MOSFETs Q5 and Q6 are connected.

Although not particularly limited, the common source line CSP to whichthe sources of the p-channel amplification MOSFETs Q7 and Q8 areconnected is provided with an n-channel power MOSFET Q16 for overdriveprovided in the cross area 18 and an n-channel power MOSFET Q15 forsupplying the internal voltage VDLA. As a voltage for overdrive,although not particularly limited, the source voltage VCC supplied froman external terminal is used. Alternately, to lessen the dependency onthe source voltage VCC of the sense amplifier operation speed, thevoltage may be obtained from the source of the n-channel MOSFET havingthe gate to which VPP is applied and the drain to which the sourcevoltage VCC is supplied and slightly decreased.

An activate signal SAP1 for sense amplifier overdrive to be supplied tothe gate of the n-channel power MOSFET Q16 has the same phase as that ofan activate signal SAP2 to be supplied to the gate of the n-channelMOSFET Q15, and SAP1 and SAP2 are set to the high level in timesequence. Although not particularly limited, the high level of SAP1 andSAP2 is equal to the step-up voltage VPP level. That is, since thestep-up voltage VPP is about 3.6V, the n-channel MOSFETs Q15 and Q16 canbe sufficiently turned on. After the off state of the MOSFET Q16 (lowlevel of the signal SAP1), by the on state of the MOSFET Q15 (high levelof the signal SAP2), a voltage corresponding to the internal voltageVDLA can be outputted from the source side.

The input/output node of the unit circuit of the sense amplifier isprovided with a precharge (equalize) circuit including an equalizeMOSFET Q11 for short-circuiting a complementary bit line and switchMOSFETs Q9 and Q10 for supplying a half precharge voltage VBLR to acomplementary bit line. A precharge signal PCB is commonly supplied tothe gates of the MOSFETs Q9 to Q11. Although not shown, in a drivercircuit for generating the precharge signal PCB, an inverter circuit isprovided in the cross area to make the driver circuit start at highspeed. Specifically, at the time of start of memory access, prior to aword line selection timing, the MOSFETs Q9 to Q11 constructing theprecharge circuit are switched at high speed via inverter circuitsprovided so as to be spread in the cross area.

In the cross area 18, an IO switch circuit IOSW (switch MOSFETs Q19 andQ20 for connecting a local IO and a main IO) is placed. Other than thecircuits shown in FIG. 3, as necessary, a half precharge circuit for thecommon source lines CSP and CSN of the sense amplifier, a half prechargecircuit of the local input/output line LIO, a VDL precharge circuit ofthe main input/output line, spread driver circuits of shared selectionsignal lines SHR and SHL, and the like are also provided.

The unit circuit of the sense amplifier is similarly connected to thecomplementary bit lines BL and BLB in the sub array 15 on the lower sideof the diagram via shared switch MOSFETs Q3 and Q4. For example, whenthe sub word line SWL in the upper sub array is selected, the sharedswitch MOSFETs Q1 and Q2 on the upper side of the sense amplifier areturned on and the lower shared switches MOSFETs Q3 and Q4 are turnedoff. Switch MOSFETs Q12 and Q13 construct a column (Y) switch circuit.When the selection signal YS is set to the selection level (high level),the switch MOSFETs Q12 and Q13 are turned on to thereby connect theinput/output node of the unit circuit of the sense amplifier with localinput/output lines LIO1, LIO1B, LIO2, LIO2B, and the like.

Consequently, the input/output nodes of the sense amplifier areconnected to the upper complementary bit lines BL and BLB, a smallsignal of a memory cell connected to the selected sub word line SWL isamplified, and the amplified signal is transmitted to the localinput/output lines LIO1 and LIO1B via the column switch circuit (Q12 andQ13). The local input/output lines LIO1 and LIO1B extends along thesense amplifier line, that is, in the lateral direction of the diagram.The local input/output lines LIO1 and LIO1B are connected to maininput/output lines MIO and MIOB to which an input terminal of a mainamplifier 61 is connected via the IO switch circuit constructed by then-channel MOSFETs Q19 and Q20 provided in the cross area 18.

The IO switch circuit is switched by a selection signal obtained bydecoding an X address signal. The IO switch circuit may take the form ofa CMOS switch in which p-channel MOSFETs are connected to the n-channelMOSFETs Q19 and Q20 in parallel. In a burst mode of a synchronous DRAM,the column selection signal YS is switched by a counter operation,thereby sequentially switching the connection between the localinput/output lines LIO1 and LIO1B and the local input/output lines LIO2and LIO2B and two pairs of complementary bit lines BL and BLB in the subarrays.

An address signal Ai is supplied to an address buffer 51. The addressbuffer operates in a time division manner and receives an X addresssignal and a Y address signal. The X address signal is supplied to apredecoder 52 and passed through a main row decoder 11 and a main worddriver 12, thereby generating a selection signal of a main word lineMWL. Since the address buffer 51 receives the address signal Ai suppliedfrom an external terminal, the address buffer 51 is operated by thesource voltage VCC supplied from the external terminal. The predecoderis operated by the step-down voltage VDLP, and the main word driver 12is operated by the step-up voltage VPP. As the main word driver 12, alogic circuit with level converting function for receiving the predecodesignal which will be described hereinbelow is used. A column decoder(driver) 53 receives a Y address supplied by a time-divisional operationof the address buffer 51 and generates the selection signal YS.

The main amplifier 61 is operated by the step-down voltage VDLP, and asignal is outputted from an external terminal Dout via an output buffer62 operated by the source voltage VCC supplied from an externalterminal. A write signal entered from an external terminal Din isreceived via an input buffer 63 and is supplied to the main input/outputlines MIO and MIOB via a write amplifier (write driver) included in themain amplifier 61 in the diagram. At an input section of the outputbuffer 62, a level converting circuit and a logic section for outputtingan output signal of the level converting circuit synchronously with atiming signal corresponding to the clock signal are provided.

Although not particularly limited, the source voltage VCC supplied fromthe external terminal is set to 3.3V in the first embodiment, thestep-down voltage VDLP supplied to an internal circuit is set to 2.5V,and the operation voltage VDLA of the sense amplifier is set to 2.0V.The selection signal (step-up voltage) of the word line is set to 3.6V.The precharge voltage VBLR of a bit line is set to 1.0V corresponding toVDL/2, and the plate voltage VPLT is also set to 1.0V. The substratevoltage VBB is set to −1.0V. The source voltage VCC supplied from theexternal terminal may be set to a low voltage such as 2.5V. At the timeof a low source voltage VCC, the step-down voltage VDLP is set to 2.0Vand the step-down voltage VDLA is set to be lowered to about 1.8V.

FIG. 13 is a general block diagram showing an example of an SDRAMaccording to the invention. Although not particularly limited, in theSDRAM of the embodiment, a memory array 200A constructing the memorybank 0 and a memory array 200D constructing the memory bank 3 out of thefour memory banks are shown as an example. That is, the memory arrays200B and 200C corresponding to two memory banks 1 and 2 out of the fourmemory banks are not shown. Each of the memory arrays 200A to 200Dcorresponding to the four memory banks 0 to 3 has dynamic memory cellsarranged in a matrix as shown in each of the memory arrays 200A and 200Dshown in the diagram as an example. According to the diagram, selectionterminals of memory cells arranged in the same column are coupled to aword line (not shown) of each column, and data input/output terminals ofthe memory cells disposed in the same row are coupled to complementarydata lines (not shown) every row.

One of not-illustrated word lines of the memory array 200A is driven tothe selection level in accordance with a decode result of a row addresssignal by a row decoder 201A. A not-illustrated complementary data linein the memory array 200A is coupled to an I/O line 202A including asense amplifier and a column selection circuit. The sense amplifier inthe I/O line 202 a including the sense amplifier and column selectioncircuit is an amplification circuit for detecting and amplifying a smallpotential difference appearing on each complementary data line byreading data from a memory cell. The column switch circuit is a switchcircuit for selecting a complementary data line and making acomplementary I/O line conductive. The column switch circuit isselectively operated in accordance with a result of decoding the columnaddress signal by a column decoder 203A.

The memory arrays 200B and 200D are similar to the above. As shown inthe memory array 200D as an example, a row decoder 201B, an I/O line202B including a sense amplifier and a column selection circuit, and acolumn decoder 203B are provided. The complementary I/O lines areconnected to output terminals of write buffers 214A and 214B and inputterminals of main amplifiers 212A and 212B. Output signals of the mainamplifiers 212A and 212B are transmitted to the input terminal of alatch/register 213, and an output signal of the latch/register 213 isoutputted from an external terminal via an output buffer 211. A writesignal entered from an external terminal is transmitted to the inputterminals of the write buffers 214A and 214B via an input buffer 210.The external terminal is, although not particularly limited, a datainput/output terminal for outputting data D0 to D15 of 16 bits. Incorrespondence with the memory arrays 200B and 200C which are not shown,main amplifiers and write buffers similar to the above are provided.

The address signals A0 to A13 supplied from the address input terminalsare received in an address multiplex format by a column address buffer205 and a row address buffer 206. The supplied address signal is held byeach buffer. In a refresh operation mode, the row address buffer 206receives a refresh address signal outputted from a refresh counter 208as a row address signal. An output of the column address buffer 205 issupplied as preset data of a column address counter 207, and the columnaddress counter 207 outputs a column address signal as the preset dataor a value obtained by sequentially incrementing the column addresssignal to the column decoders 203A to 203D in accordance with anoperation mode designated by a command or the like which will bedescribed hereinlater.

A controller 209 shown by a dotted line receives, although notparticularly limited, external control signals such as a clock signalCLK, a clock enable signal CKE, a chip select signal CS/, a columnaddress strobe signal CAS/ (the sign/denotes that a signal to which thesign/is attached is a row enable signal), a row address strobe signalRAS/, and a write enable signal WE/ and control data from the addressinput terminals A0 to A13, and generates internal timing signals forcontrolling an operation mode of the SDRAM and an operation of thecircuit blocks on the basis of a change in level of each of the signals,timings, and the like. The controller 209 includes a mode register 10, acommand decoder 20, a timing generation circuit 30, and a clock buffer40.

The clock signal CLK is supplied via the clock buffer 40 to a clocksynchronizing circuit 50 and an internal clock is generated. Theinternal clock is used, although not particularly limited, as a timingsignal for making the output buffer 211 and the input buffer 210 active,and supplied to the timing generating circuit 30 where timing signals tobe supplied to the column address buffer 205, row address buffer 206,and column address counter 207 are generated on the basis of the clocksignal.

As the test circuit as shown by a hatched part, for example, thecomputing circuit ALIU2 and the packet decoder are assembled adjacent toan address latch included in the row address buffer 206, and thecomputing circuit ALU1 and the packet decoder are assembled in thecolumn address counter. Packet decoders are disposed in correspondencewith the command decoder 20 for generating control signals, the timinggenerating circuit 30, and the like. The function of receiving thepacket signal is added to the input buffer 210. The packet control PC isadded to the clock buffer 40.

An external input signal becomes significant synchronously with theleading edge of the internal clock signal. The chip select signal CS/instructs the start of a command input cycle by its low level. When thehigh level (chip non-selection state) of the chip select signal CS/ isset, other inputs do not have any meaning. The selection state of amemory bank and an internal operation such as a burst operation are notinfluenced by a change to the chip non-selection state. The signalsRAS/, CAS/, and WE/ have functions different from those of correspondingsignals in an ordinary dynamic RAM and become significant when a commandcycle which will be described hereinlater is defined.

The clock enable signal CKE is a signal for instructing the validity ofthe next clock signal. When the signal CKE is at the high level, theleading edge of the next clock signal is valid. When the signal CKE isat the low level, the leading edge of the next clock signal is invalid.In the read mode, in the case of providing an external control signalOE/ for performing output enable control on the output buffer 211, thesignal OE/ is also supplied to the controller 209. For example, when thesignal is at the high level, the output buffer 211 is set in a highoutput impedance.

The row address signal is defined by the level of A0 to A11 in a rowaddress strobe bank active command cycle which will be describedhereinlater synchronized with the leading edge of the clock signal CLK(internal clock signal).

The address signals A12 and A13 are regarded as bank selection signalsin the row address strobe bank active command cycle. Specifically, by acombination of A12 and A13, one of the four memory banks 0 to 3 isselected. The control of selecting a memory bank can be carried out by,although not particularly limited, a process such as activation of onlya row decoder on the selected memory bank side, selection of no columnswitch circuit on the not-selected memory bank side, connection to theinput buffer 210 and output buffer 211 only on the selected memory bankside, or the like.

The column address signal is defined by the level of A0 to A7 in a cycleof a read or write command (a column address read command or a columnaddress write command which will be described hereinlater) synchronizedwith the leading edge of the clock signal CLK (internal clock). That is,the column address signal is used to select one of the 256 pairs ofcomplementary bit lines provided for the sub array as shown in FIG. 11.A column address defined in such a manner is used as a start address ofa burst access.

Typified operation modes of an SDRAM instructed by commands will now bedescribed.

(1) Mode Register Set Command (REG)

This is a command for setting the mode register 30. The command isdesignated by the low level of CS/, RAS/, CAS/, or WE. Data to be set(register set data) is supplied via A0 to A11. Although not particularlylimited, the register set data is burst length, CAS latency, write mode,and the like. Although not particularly limited, burst lengths which canbe set are 1, 2, 4, 8, and a full page, CSA latency which can be set is1, 2, and 3, and write modes which can be set are burst write and singlewrite modes.

The CAS latency denotes the number of cycles of an internal clock signalspent in a period from the trailing edge of the signal CAS/ until theoutputting operation of the output buffer 211 in the reading operationinstructed by the column address read command which will be describedhereinlater. The internal operation time for reading data is necessaryuntil read data is determined. The CAS latency is used to set theinternal operation time in accordance with the use frequency of aninternal clock signal. In other words, in the case of using an internalclock signal of a high frequency, the CAS latency is set to a relativelylarge value. In the case of using an internal clock signal of a lowfrequency, the CAS latency is set to a relatively small value.

(2) Bank Active Command (ACTV)

This is a command for instructing a row address strobe and makingselection of a memory bank by A12 and A13 valid, and is instructed bythe low level of CS/ and RAS/ and the high level of CAS/ and WE/. Anaddress supplied to A0 to A11 at this time is captured as a row addresssignal and a signal supplied to A12 and A13 is captured as a memory bankselection signal. The capturing operation is performed synchronouslywith the leading edge of the internal clock signal as described above.For example, when the command is designated, a word line in a memorybank designated by the command is selected, and a memory cell connectedto the word line is made conductive by corresponding complementary datalines. In the testing operation, A12 and A13 are made invalid and fourmemory banks are simultaneously accessed.

(3) Read Command (READ)

The command is a command necessary to start the burst reading operationand is a command for giving an instruction of the column address strobe.The command is instructed by the low level of CS/ and CAS/ and the highlevel of RAS/ and WE/. A column address supplied to A0 to A7 (in thecase of a 16-bit configuration) is captured as a column address signal.The column address signal captured is supplied as a burst start addressto the column address counter 207. In the burst reading operationinstructed by the signal, a memory bank and a word line have beenselected in the preceding row address strobe bank active command cycle.The memory cells of the selected word line are sequentially selected andcontinuously read in accordance with an address signal outputted fromthe column address counter 207 synchronously with the internal clocksignal. The number of data continuously read is the number designated asthe burst length. Reading of data from the output buffer 211 is startedafter the number of cycles of the internal clock signal specified by theCAS latency.

(4) Write Command (WRIT)

When the burst write mode is set in the mode register 10 as a mode ofthe writing operation, the write command is necessary to start the burstwrite operation. When the single write mode is set in the mode register10 as a mode of the writing operation, the write command is necessary tostart the single write operation. By the command, the column addressstrobe in the single write or burst write mode is instructed. Thecommand is issued by the low level of CS/, CAS/ and WE/ and the highlevel of RAS/. An address supplied to A0 to A7 is captured as a columnaddress signal. The column address signal captured is supplied as aburst start address to the column address counter 207 in the burst writemode. The procedure of the burst write operation instructed by thesignal is similar to that of the burst read operation. In the writingoperation, however, there is no CAS latency. Capturing of write data isstarted from the column address write command cycle.

(5) Precharge Command (PRE)

This is a command to start an operation of precharging a memory bankselected by A12 and A13 and is instructed by the low level of CS/, RAS/,and WE/, and the high level of CAS/.

(6) Automatic Refresh Command (CBR)

This is a command necessary to start automatic refresh and is instructedby the low level of CS/, RAS/, and CAS/, and the high level of WE/ andCKE.

(7) Burst Stop (BST)

This is a command necessary to stop the burst operation in a full pageon all of memory banks. The command is ignored in burst operationsexcept for the burst operation in a full page. The command is instructedby the low level of CS/ and WE/ and the high level of RAS/ and CAS/.

(8) No Operation Command (NOP)

This is a command for instructing that no substantial operation isperformed and is instructed by the low level of CS/ and the high levelof RAS/, CAS/, and WE/.

In the SDRAM, while a burst operation is performed in one memory bank,when another memory bank is designated and the row address strobe bankactive command is supplied, without exerting an influence on theoperation in the memory bank being subjected to the operation, a rowaddress operation in the another memory bank can be performed. Forexample, the SDRAM has means for holding data, an address, and a controlsignal supplied from the outside. Although not particularly limited, thedata to be held, particularly, an address and a control signal are heldin each memory bank. Alternately, data of one word line in a memoryblock selected in the row address strobe bank active command cycle ispreliminarily latched in the latch/register 213 for reading operationprior to a column operation.

For example, as long as the data D0 to D15 does not collide with eachother at the data input/output terminal of 16 bits, during execution ofa command of which process is not finished yet, the precharge commandand the row address strobe bank active command can be issued to a memorybank different from the memory bank being processed by the command tostart an internal operation in advance. The SDRAM in the embodimentperforms the memory access on the 16-bit unit basis, has addresses ofabout 1M in which X addresses are A0 to A11 and Y addresses are A0 toA7, and includes four memory banks. Consequently, the SDRAM has astorage capacity of about 64 Mbits (=1 M×4 banks×16 bits) as a total.

FIG. 14 is a schematic configuration diagram showing an example of atest system according to the invention.

In a semiconductor memory device according to the invention, asdescribed above, the number of electrodes for a test is set to a smallvalue such as 15. For the small number of electrodes, consequently, anintermediate layer provided with POGO pins is prepared. Although notparticularly limited, the intermediate layer is provided with POGO pinsto come into contact with the pads for test on all of memory chipsformed on a wafer. By the arrangement, electric contact can besimultaneously made to all of the memory chips on a wafer.

The POGO pins are contact pins protruding upward and downward from asubstrate and moving in the axial direction by a spring. The POGO pinson the lower side of the intermediate layer come into electrical contactwith pads for test of memory chips formed on the wafer. The intermediatelayer functions as a contact pitch converting board and has pinsprotruding upward which comes into electrical contact with a batchtesting board provided above via the pins.

On the batch testing board, a DC (DC control/measuring chip), a controlchip such as a microcomputer for controlling the whole, and a controlprogram chip such as an EEPROM in which the control program is storedare mounted. The three chips construct a testing circuit set. Aplurality of testing circuit sets are mounted. The memory chips formedon the wafer are divided into a plurality of sets in correspondence withthe plurality of testing circuits.

For the batch testing board, a central control unit is provided. Acontrol program according to the function of the memory chip or the likeis supplied from the central control unit to each of the testingcircuits on the batch testing board, and a batch test on the memorychips formed on the wafer can be realized via the batch testing circuit.

When a plurality of the batch testing boards and a plurality of contactpitch converting boards are provided for the central control unit, aprobing test can be conducted simultaneously on a plurality of wafers.

A wafer may be divided into a plurality of areas, and the intermediatelayer and the batch testing circuit may conduct a simultaneous test onlyto memory chips provided in the divided area. In the case of conductinga batch test on the divided wafer, a test may be conducted on the otherareas in a time division manner.

The actions and effects obtained from the embodiments are as follows.

(1) A memory circuit having a memory cell array in which a plurality ofmemory cells are provided at intersection points of a plurality of wordlines and a plurality of bit line pairs and a peripheral circuit forperforming an operation of selecting an address is provided with: acomputing circuit for generating an address signal for test of thememory circuit; a packet decoder for designating the kind of computationto the computing circuit; and an input circuit for supplying a testsignal comprising a plurality of bits for designating a testingoperation to the packet decoder. Consequently, an effect such that thenumber of pads for test is reduced by adding a simple circuit and thenumber of chips to be simultaneously measured is largely increased,thereby enabling test time to be shortened is produced.

(2) The input circuit uses the number of bits smaller than the pluralityof bits adapted to a memory access as the test signal in an input bufferadapted to the memory access on the unit basis of a plurality of bits.Therefore, an effect such that a test mode can be set and a test resultcan be outputted by using the smaller number of electrodes is obtained.

(3) The computing circuit and the packet decoder corresponding to thecomputing circuit are provided in correspondence with each of an Xaddress signal and a Y address signal and are provided adjacent tocircuits for holding the address signals at the time of memory access,thereby obtaining an effect such that the empty area in an existingcircuit can be effectively used and higher packing density and higheroperation speed can be realized.

(4) By further providing a packet control circuit for setting an inputsignal supplied via the input circuit as a test signal by a combinationof predetermined control signals, an effect such that the circuit can beshared is produced.

(5) An operation control is performed on the semiconductor memory deviceby a command designated by a combination of a plurality of controlsignals and an address signal as necessary, a plurality of packetdecoders including not only the packet decoder adapted to the computingcircuit, but also a packet decoder for controlling a timing generationcircuit, and a packet decoder adapted to control a command decoder fordecoding the command are provided adjacent to the respective circuits,and the test signals are connected in parallel. Consequently, an effectsuch that the empty area in an existing circuit can be effectively usedand higher packing density and higher operation speed can be realized isobtained.

(6) The semiconductor memory device is a synchronous dynamic RAM havingfour memory banks, and has a plurality of input/output circuits forinputting/outputting a plurality of data bits corresponding to a unit ofmemory access; and the test signal comprises four bits, and fourinput/output circuits out of input/output circuits corresponding to theplurality of data bits are used as an input circuit for receiving a testsignal and an output circuit for outputting test results correspondingto the four memory banks. In such a manner, an effect such that commandsoptimum for a testing operation can be generated and a test result canbe obtained by using the smaller number of pads is produced.

(7) By further providing a packet control circuit for setting an inputsignal supplied via the input circuit as a test signal by a combinationof a clock signal and a control signal, an effect such that the existinginput/output circuit can be effectively utilized is obtained.

(8) A command having a high use frequency of the synchronous dynamic RAMis used as a first format including only a test signal supplied firstout of the four-bit test signals, a command having a use frequency lowerthan that of the first format out of commands of the synchronous dynamicRAM is used as a second format including a test signal supplied in twocycles out of the four-bit test signals, and a command for settingvarious registers provided for the synchronous dynamic RAM is used as athird format including a test signal supplied in four cycles out of thefour-bit test signals. Consequently, an effect such that reduction inthe number of terminals for test and various testing operations can berealized without deteriorating the speed of the testing operations isobtained.

(9) The first format includes a no-operation command, a bank activecommand, a read command, and a write command, and each of the bankactive command, the read command, and the write command has a pluralityof address controls performed by using the computing circuit.Consequently, an effect such that a testing operation can be set atspeed as high as a normal operation is obtained.

(10) The second format instructs reference to a test signal to besupplied next in test signals supplied in the first cycle, and decodesthe input test signal and generates the plurality of commands in thesecond cycle. Thus, an effect such that operation setting necessary fora testing operation can be assured without increasing substantial testtime is produced.

(11) The third format instructs reference to a test signal to besupplied next by using the test signal supplied in the first cycle, setsthe kind of a register by the test signal supplied in the second cycle,generates a register command by the test signal supplied in the thirdcycle, and operates the selected register by a test signal supplied inthe fourth cycle. Consequently, an effect such that operation settingnecessary for a number of testing operations can be assured with asimple circuit is obtained.

(12) The packet control circuit generates a first clock and a secondclock obtained by dividing the frequency of the clock signal to thehalf, the first and third cycles for inputting the test signal areperformed by the first clock, and the second and fourth cycles forinputting the test signal are performed by the second clock.Consequently, an effect such that various testing operations can be setwith a simple circuit is obtained.

(13) A test system for a wafer on which a plurality of memory chips aremounted, each of the memory chips including: a memory cell array inwhich a plurality of memory cells are provided at intersection points ofa plurality of word lines and a plurality of bit line pairs and aperipheral circuit for performing an operation of selecting an address,a computing circuit for generating an address signal for test of thememory circuit, a packet decoder for designating the kind of computationto the computing circuit, and an input circuit for supplying a testsignal comprising a plurality of bits for designating a testingoperation to the packet decoder. A plurality of POGO pins to beelectrically contacted with which one ends of pads related to the testof a plurality of memory chips formed on the wafer are connected with atesting board on which a semiconductor integrated circuit device forcontrol for generating various signals for a test on the plurality ofmemory chips is mounted via a contact pitch converting board having aplurality of POGO pins which come into electric contact with the otherends, and a central control unit for supplying a test control signal tothe semiconductor integrated circuit device for control provided on thetesting board is provided, thereby obtaining an effect such that aplurality of memory chips in electric contact can be measuredsimultaneously.

(14) The intermediate board comes into electrical contact with thetest-related pads of all of memory chips formed on the wafer, and aplurality of semiconductor integrated circuit devices for controlprovided on the testing board are used to conduct a batch probing teston all of memory chips formed on the wafer, thereby obtaining an effectsuch that wafer batch testing can be realized.

Although the invention achieved by the inventor has been specificallydescribed on the basis of the embodiments, obviously, the invention isnot limited to the embodiments but can be variously modified. Forexample, as the input circuit for test, an address input circuit may beused. The number of bits of a packet signal of a test signal may be notonly four as described above but also three or five. The semiconductormemory device is not limited to an SDRAM as described above but can be adynamic RAM controlled by RAS/, CAS/, and WE/, or a static RAM.

INDUSTRIAL APPLICABILITY

The present invention can be widely applied to various semiconductormemory devices and test systems as described above.

What is claimed is:
 1. A semiconductor memory device comprising: amemory circuit having a memory cell array in which a plurality of memorycells are provided at intersection points of a plurality of word linesand a plurality of bit line pairs and a peripheral circuit whichperforms an operation of selecting an address; an arithmetic circuitwhich generates an address signal to test said memory circuit; a firstpacket decoder which designates the kind of operation to said arithmeticcircuit; and an input and output circuit which supplies a test signalcomprising a plurality of bits which designate a testing operation tosaid first packet decoder.
 2. A semiconductor memory device according toclaim 1, wherein said input and output circuit uses a number of bits fora test signal which is smaller than the plurality of bits needed for amemory access to said memory circuit.
 3. A semiconductor memory deviceaccording to claim 1, wherein said arithmetic circuit and the packetdecoder corresponding to said arithmetic circuit are provided incorrespondence with each of an X address signal and a Y address signaland are provided adjacent to circuits which hold the address signals atthe time of memory access.
 4. A semiconductor memory device according toclaim 2, further comprising a packet control circuit which sets an inputsignal supplied via said input and output circuit as a test signal by acombination of predetermined control signals.
 5. A semiconductor memorydevice according to claim 1, further comprising: a second packet decoderto control a timing generation circuit; and a third packet decoder tocontrol a command decoder to decode said command, wherein an operationcontrol is performed by a command designated by a combination of aplurality of control signals and an address signal, and wherein saidfirst, second and third packet decoders are connected in parallel to asignal line through which said test signal is transmitted.
 6. Asemiconductor memory device according to claim 5, wherein said memorycircuit is a synchronous dynamic RAM having four memory banks, whereinsaid input and output circuit has a plurality of input/output circuitseach inputting/outputting a plurality of data bits corresponding to aunit of memory access, wherein said test signal comprises four bits, andwherein four of said plurality of input/output circuits are used as aninput circuit to receive a test signal and as an output circuit tooutput test results corresponding to said four memory banks.
 7. Asemiconductor memory device according to claim 6, further comprising apacket control circuit which sets an input signal supplied via saidinput circuit as a test signal by a combination of a clock signal and acontrol signal.
 8. A semiconductor memory device according to claim 7,wherein a command having a high use frequency of said synchronousdynamic RAM is used as a first format including only a test signalsupplied first out of said four-bit test signals, wherein a commandhaving a use frequency lower than that of said first format out ofcommands of said synchronous dynamic RAM is used as a second formatincluding a test signal supplied in two cycles out of said four-bit testsignals, and wherein a command to set various registers provided forsaid synchronous dynamic RAM is used as a third format including a testsignal supplied in four cycles out of said four-bit test signals.
 9. Asemiconductor memory device according to claim 8, wherein said firstformat includes a no operation command, a bank active command, a readcommand, and a write command, and wherein each of said bank activecommand, said read command, and said write command has a plurality ofaddress controls performed by using said arithmetic circuit.
 10. Asemiconductor memory device according to claim 8, wherein said secondformat instructs reference to a test signal to be supplied next by usingthe test signal supplied in the first cycle, decodes the test signalsupplied in the second cycle, and generates said plurality of commands.11. A semiconductor memory device according to claim 8, wherein saidthird format: instructs reference to a test signal to be supplied nextby using the test signal supplied in the first cycle, sets the kind of aregister by the test signal supplied in the second cycle, generates aregister command by the test signal supplied in the third cycle, andoperates said selected register by a test signal supplied in the fourthcycle.
 12. A semiconductor memory device according to claim 8, whereinsaid packet control circuit generates a first clock and a second clockobtained by dividing the frequency of said clock signal in half, whereinsaid first and third cycles to input said test signal are performed bysaid first clock, and wherein said second and fourth cycles to inputsaid test signal are performed by said second clock.
 13. A test systemfor a wafer on which a plurality of memory chips are mounted,comprising: an intermediate board having a plurality of POGO pins withwhich one ends of pads related to said test of a plurality of memorychips formed on said wafer come into contact; a testing board having anelectrode coming into electrical contact with the other ends of theplurality of POGO pins provided for said intermediate board, on which asemiconductor integrated circuit device for control to generate varioussignals for a test on the plurality of memory chips is mounted; and acentral control unit which supplies a test control signal to thesemiconductor integrated circuit device for control provided on saidtesting board, wherein each of the memory chips comprises a memorycircuit, an arithmetic circuit which generates an address signal to testsaid memory circuit, a packet decoder which designates the kind ofoperation to said arithmetic circuit, and an input circuit whichsupplies a test signal comprising a plurality of bits to designate atesting operation to said packet decoder, and wherein said memorycircuit includes a memory cell array in which a plurality of memorycells are provided at intersection points of a plurality of word linesand a plurality of bit lines pairs, and a peripheral circuit to performan operation selecting an address.
 14. A test system according to claim13, wherein said intermediate board comes into electrical contact withsaid test related pads on all of memory chips formed on said wafer, andwherein a plurality of semiconductor integrated circuit devices forcontrol provided on said testing board are used to conduct a batchprobing test on all of memory chips formed on the wafer.